This document relates in general to integrated circuits and methods of fabrication. More specifically, this document relates to back end of line (BEOL) patterning.
Typical integrated circuits are formed by first fabricating individual semiconductor devices using processes referred to generally as the front end of line (FEOL). Thereafter, the individual devices on the integrated circuit are interconnected by forming the wiring of the wafer using processes referred to generally as the back end of line (BEOL). BEOL processes generally include the formation of contacts, insulating layers, metal layers, and bonding sites for chip-to-package connections.
A basic design construct of BEOL processes is the formation of a staggered configuration of vias or block mask structures, whereby the shapes are placed on a non-orthogonal array grid. Such structures can be challenging to image as feature sizes become smaller. In particular, the via is supposed to be constrained by the sidewalls of the line, which might not happen in the real-world applications.